`timescale 1ns/1ns
module mux8_to_1_tb;
	reg[7:0] input_data;
	reg[2:0] s;
	wire out;
	
	mux8_to_1 E(.input_1(input_data[0]),.input_2(input_data[1]),
	.input_3(input_data[2]),.input_4(input_data[3]),
	.input_5(input_data[4]),.input_6(input_data[5]),
	.input_7(input_data[6]),.input_8(input_data[7]),
	.s1(s[0]),.s2(s[1]),.s3(s[2]),.output_data(out)); 
	
	initial begin
		input_data = 8'b10101010;
		s = 3'b000;#100;
		s = 3'b001;#100;
		s = 3'b010;#100;
		s = 3'b011;#100;
		s = 3'b100;#100;
		s = 3'b101;#100;
		s = 3'b110;#100;
		s = 3'b111;#100;
	end
endmodule
